Single Board Decommutator - SBD001 - GDP Space Systems - Telemetry Systems, Synchronizers, BERTS, Demodulaters, Modulators, Receivers, Frame Synchronizers, decommutator, Simulators

The SBD001 module is a general-purpose adaptive strategy PCM Frame Synchronizer / Data Decommutator. It accepts digital serial clock and NRZ-L data at rates up to 16 Megabits per second and returns decommutated data samples in onboard dual ported ping-pong memory buffers and to a parallel output port. Contained on a single ISA Bus compatible card, the SBD001 is a low-cost, high performance device for acquiring IRIG telemetry data into a personal computer.

Features

Single ISA Bus Slot
Bit Rate 1 bps Through 16 Mbps
IRIG Class I & II
64 Bit Sync Pattern W/ Mask
Adaptive Sync Strategy
Slip Window
Automatic Polarity Correction
262,144 Bits

16384 Words Per Frame

4 To 16 Bits Per Word
Subframe Synchronization

ID Count
Recycle Pattern

Word-By-Word Data Decommutation

Bits Per Word
Msb/Lsb
Parity Strip
Pass/Drop Editing

Parallel Data Output

All Or Selected Data
Word and Frame Number

On-Board 16 K x 16 Bit Ping-Pong Data Buffers

Accessed As Memory On The ISA Bus

End Of Buffer Interrupt

Each word in the telemetry frame is defined by Bits per Word, Data Input Orientation (MSB or LSB received first), Pass/Drop from the output stream and Parity Strip On/Off, MSB/LSB of reconstructed word.

The Dual-Ported RAM may be setup to operate in one of three modes: Current Value Table (CVT) - single minor frame; Single-Frame Parameter Array (SFPA) - ping-pong buffer each end of frame; Multi-Frame Parameter Array (MFPA) - ping-pong buffers each 'n' end of frames.

The parallel output is provided on a 50-pin connector located on the top of the board. This connector contains Data, Word Number, Frame Number, Frame & S/F Status, Word Strobe for Words selected for output, Frame Strobe, Subframe Strobe.

The data output is either all words in the frame or only the words selected by the Pass bit in the Decommutation Control Memory.


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The SBD001 module is a general-purpose adaptive strategy PCM Frame Synchronizer / Data Decommutator. It accepts digital serial clock and NRZ-L data at rates up to 16 Megabits per second and returns decommutated data samples in onboard dual ported ping-pong memory buffers and to a parallel output port. Contained on a single ISA Bus compatible card, the SBD001 is a low-cost, high performance device for acquiring IRIG telemetry data into a personal computer.
Features
Single ISA Bus Slot Bit Rate 1 bps Through 16 Mbps IRIG Class I & II 64 Bit Sync Pattern W/ Mask Adaptive Sync Strategy Slip Window Automatic Polarity Correction 262,144 Bits 16384 Words Per Frame 4 To 16 Bits Per Word Subframe Synchronization ID Count Recycle Pattern	Word-By-Word Data Decommutation Bits Per Word Msb/Lsb Parity Strip Pass/Drop Editing Parallel Data Output All Or Selected Data Word and Frame Number On-Board 16 K x 16 Bit Ping-Pong Data Buffers Accessed As Memory On The ISA Bus End Of Buffer Interrupt

Each word in the telemetry frame is defined by Bits per Word, Data Input Orientation (MSB or LSB received first), Pass/Drop from the output stream and Parity Strip On/Off, MSB/LSB of reconstructed word. The Dual-Ported RAM may be setup to operate in one of three modes: Current Value Table (CVT) - single minor frame; Single-Frame Parameter Array (SFPA) - ping-pong buffer each end of frame; Multi-Frame Parameter Array (MFPA) - ping-pong buffers each 'n' end of frames. The parallel output is provided on a 50-pin connector located on the top of the board. This connector contains Data, Word Number, Frame Number, Frame & S/F Status, Word Strobe for Words selected for output, Frame Strobe, Subframe Strobe. The data output is either all words in the frame or only the words selected by the Pass bit in the Decommutation Control Memory.