The GDP Model BSM001 PCM Bit Synchronizer is a state-of-the-art high-performance device that is designed to extract usable digital data from a noise contaminated signal environment. The optimized digital design of this unit affords the highest performance characteristics currently available.

Features

• Bit Rates
  • 40 bps to 10 Mbps (std)
  • 40 bps to 20 Mbps (opt)
• Performance within 1 dB of theory
• Auto Bit Rate Scan
• Loop bandwidth settings from 0.03%
• Accepts NRZ-L/M/S, RNRZ, BiØ-L/M/S, DM-M/S codes

• 4 Input Sources
• Status Indicators for Sync and Input Signal Present
• Randomizer/Derandomizer lengths 2N - 1: N = 9, 11, 15, 17, 20, 23
• Viterbi Decoder
• Frame Pattern Detector
• Fully Controlled from the VME Bus
• 6 U VME Form-factor

The BSM001 is capable of maintaining synchronization with the signal of interest to Eb/No of -1 dB when the signal transition density is 50%. When searching for the signal, acquisition is attainable within as few as 40 bits. The unit maintains synchronization for a period of at least 128 bit periods without a signal transition.

Encoded data streams are processed to expose the raw information. Randomized data is decoded to its native form by a pseudo-random decoder that handles lengths of 2 raised to the power 9, 11, 15, 17, 20 or 23. Both forward and reverse sequences are accommodated. Additionally, a Viterbi decoder (constraint length 7 rate 1/2) is included.

When the input bit rate is expected to be changing, use the Auto Bit Rate Scan feature. Up to nine bit rates are programmable. The bit synchronizer automatically finds the appropriate setting from the list and locks to the input signal. To add accuracy to the lock decision, the Viterbi decoder and / or the Frame Pattern Detector may be included.

To further assure synchronization to the intended data stream, the Frame Pattern Detector may be invoked. Up to a 32-bit long pattern is detected. Maintaining synchronization with this pattern at the programmed repetition rate produces a lock signal.