The GDP BER005 Bit Error Rate Tester (BERT) fills the need for high performance link verification and qualification at an affordable price. The user is provided with totally independent transmit and receive functions to allow rapid fault isolation and data link characterization through realtime bit contiguous test. Features such as an internal DDS frequency synthesizer and IRIG Code convertor make the BER005 especially suited to the test and evaluation of PCM Telemetry data link systems and components.

The BER005 offers the following measurements: Accumulated Bit Errors, Measured Bit Error Rate, Accumulated Block Errors, Accumulated Errorfree Seconds, Accumulated Error Seconds, Measured error Symmetry, Accumulated Bit Count Integrity loss (Bit Slips), Measured Transmit and Receive clock rate, BER History.

Features

• 1 bps to 25 Mbps Operation
• Independent Transmitter and Receiver
• Bit, Block and Second Tests
• Symmetry & Bit Slip Tests
• Twelve Selectable PRN Patterns
• 32 bit/24 bit user programmable patterns
• TX, RX Frequency Measurements
• Internal DDS Frequency Synthesizer
• IRIG Code Conversion
• TTL, ECL, RS422, RS232, Bipolar Data and Clock Interfaces
• VME Bus Control
• Single slot width, 6U x 160 mm VME card

The BER005 Bit Error Rate Tester gives the superior data link transmission test capability in a module based on the industry-standard VME-bus. A fully programmable DDS frequency synthesizer allows transmit clock generation from I bps to 25 Mbps, selectable to 1 bps resolution. A flexible interface structure, which provides IRIG code convertors for both input and output data, allows the BER005 to fully support test and evaluation of telemetry receive and processing systems.

A microprocessor resident on the BERT module controls the transmit and receive circuits through user commands issued via the VME interface. Communication is accomplished via a dual-ported RAM architecture. All high-speed functions such as data generation, PN synchronization, error detection and accumulation are provided by hardware. Lower speed functions such as test data accumulation and formatting for the VME bus interface are provided by the embedded microprocessor.

Data patterns are selectable from a list of PRN sequences or fixed 32/24 bit patterns programmable by the user. Transmit output data encoding and receiver input decoding is provided for all IRIG-106 codes.

The system under test can be stressed adding an optional clock jitter. The Transmit data output can be jittered at frequencies up to 10 MHz and deviations of up to +/- 180o. A separate Analog output for Send Data is also provided. Signal level and offset are programmable. External Noise input can be mixed with the Analog output for added test capability.

Applications

In a telemetry ground station or in a satellite ground data handling system, the BER005 provides the capability to perform link quality analysis and overall system checkout. A single BER005 provides both data transmit and data receive sections to support loopback verification testing. The user may program the BER005 for a particular data pattern and bit rate. Independent transmitter and receiver functions permit full duplex end-to-end tests using a BERT at each end. Transmit and receive test parameters can be set the same or different for each direction.

By utilizing upconverters and transmitters the user can convert the baseband information to the appropriate frequency band and exercise the entire ground receive system from antenna through bit synchronizer. The recovered data will be synchronized by the BER005 which will accumulate test data for user analysis.

The BER005 provides high performance functionality and ease-of-use in a single VME card. These features coupled with good cost/performance ratio make the BER005 an excellent addition to any telemetry system.