![]() |
© 2004 GDP Space Systems - a division of Delta Information Systems, Inc. |
[ Synchronizers / Decommutators | Bit Synchronizers ]
|
The GDP Model 266 Multi-Channel PCM Bit Synchronizer houses up to eight high-performance bit synchronizer modules. The optimized digital design of this unit affords the highest performance characteristics currently available. |
|
Features |
|
|
|
![]() |
|
![]() |
|
|
The Model 266 is capable of maintaining synchronization with the signal to Eb/No of 0.5 dB when the signal transition density is 50%. Signal, acquisition is attainable within a small number of bits. In the absence of transitions, synchronization is maintained for at least 128 bit periods. Encoded data streams are processed to expose the raw information. Randomized data is decoded to its native form by a pseudo-random decoder that handles lengths of 2 raised to the power 9, 11, 15, 17, 20 or 23. Both forward and reverse sequences are accommodated. Additionally, a Viterbi decoder (constraint length 7 and rate 1/2) is included to handle this convolutional code up to bit rates of 10 Mbps. To further assure synchronization to the intended data stream, a Frame Pattern Detector may be invoked. Up to a 32-bit long pattern is detected. Maintaining synchronization with this pattern at the programmed repetition rate produces a lock status signal. When the input bit rate is expected to be changing, use the Auto Bit Rate Scan feature. Up to nine bit rates are programmable. The bit synchronizer automatically finds the appropriate setting from the list and locks to the input signal. To add accuracy to the lock decision, the Viterbi decoder and / or the Frame Pattern Detector are included in the test. Using the Compact PCI form-factor, all modules in the Model 266 are capable of being replaced without removing power from the unit. Upon inserting a new module, all previous settings are restored. |
|