The GDP Model 265 PCM Bit Synchronizer is a state-of-the-art high-performance device that is designed to extract usable digital data from a noise contaminated signal environment. The optimized digital design of this unit affords the highest performance to price characteristics currently available.

Features

• Bit Rates to 20 Mbps
• Performance within 1 dB
  of theory
• Loop bandwidth settings
  from 0.5% to 1.6%
• Accepts NRZ-L/M/S,
  BiØ-L/M/S, DBiØ-M/S,
  DM-M/S codes

• 4 Input Sources
• Viterbi Decoder
• Status Indicators for Sync
  and Input Signal
• Randomizer/Derandomizer lengths:
  9, 11, 15, 17, 23
• Remote Control via RS-232 or
  IEEE-488

The Model 265 is capable of maintaining synchronization with the signal of interest to Eb/No of –2 dB when the signal transition density is 50% or greater. When searching for the signal, acquisition is attainable within as few as 40 bits. NRZ codes can produce long strings of ones or zeros. When this occurs, the unit maintains synchronization for a period equivalent to 128 bit periods.

Encoded data streams are processed to expose the raw information. Randomized data is decoded to its native form by a pseudo-random decoder that handles lengths of 2 raised to the power 9, 11, 15, 17 or 23. Both forward and reverse sequences are accommodated. Additionally, a Viterbi decoder (constraint length 7 and rate 1/2) is included to handle this convolutional code up to bit rates of 10 Mbps.