Bit Synchronizers

Model BSM202 Dual PCM Bit Synchronizer on PCI Card
Model BSM202 Dual PCM Bit Synchronizer on PCI Card

The GDP Model BSM202 is a Dual Channel PCM Bit Synchronizer on a single PCI card (single channel configurations also available). The BSM202 is a state-of-the-art high performance device that is designed to extract usable digital data from a noise contaminated signal environment. The optimized digital design of this unit affords the highest performance characteristics currently available.

The BSM202 is capable of maintaining synchronization with the signal of interest to Eb/No of -3 dB when the signal transition density is 50%. When searching for the signal, acquisition is attainable in less than 50 bits. The unit is very robust and can maintain synchronization for a period of at least 256 bit periods without a transition.

The standard IRIG randomizer/derandomizer for both forward and reverse sequences is provided. CCITT V.35 and V.36 scrambling/descrambling is also provided. A variety of Viterbi decoders are available including R1/2 K7 (Std), R3/4 K7 andR1/3 k7 (please inquire for other FEC options).

To assure synchronization to the intended data stream, the Frame Pattern Detector may be invoked. Up to a 64-bit long pattern is detected. Maintaining synchronization with this pattern at the programmed repetition rate and synchronization strategy produces a lock signal. An Automatic Polarity Correction (APC) mode is also provided for inverted data.

The BSM202 includes several unique features to determine the quality of the data. The first is an Eb/No (Signal Quality) measurement. From this measurement, the error rate of the data can be determined. The BSM202 also measured errors in the frame synchronizer pattern, as well as errors in the viterbi stream when these modes are enabled. A bit-error-rate (BERT) function is also provided. This allows link test in a short loop-back to verify proper operation of the module, or long loop-back to measure performance of the link. An advanced lock detector ensures a solid lock indication for the module.

The Auto Scan feature is available to scan the input for up to 8 combinations of bit rates, input codes and frame patterns (per Bit Sync). When one of the signals is present, the Bit Sync automatically locks onto it and recovers the data and clock.

  1. Dual Channel ( Single Channel Configurations available)
  2. Bit Rates
  3.      • 5 bps to 20 Mbps (std)
         • 5 bps to 40 Mbps (opt)
  4. Performance within 1 dB of theory
  5. Loop bandwidth settings from 0.01% to 1.6%
  6. Tracking up to 15%
  7. Accepts NRZ-L/M/S, RNRZ, BiØ-L/M/S, DM-M/S MDM
  8. 2 Input Sources per Channel
  9. Status Indicators for Sync and Input Signal Present
  10. Randomizer / Derandomizer
  11. Scrambler/Descrambler CCITT V.35/36
  12. Viterbi Decoder
  13. Frame Pattern Detector
  14. Signal Quality Status
  15.      • Eb/No Measurement
         • Frame Sync Pattern Error Count (BER Status)
         • Viterbi Error Count
         • BERT/ PRN BER Measurement
  16. Advanced Lock Detection
  17. Auto Scan (Optional)
  18. Fully Controlled via RS-232 or RS-485 Remote Port or via from the PCI Bus
  19. PCI Form-factor (one slot)
  20. Additional Input & Output Options Available (Extended I/O)
Inputs, each Bit Sync
Analog Inputs
Up to 2 Inputs per Bit Sync- 50 ohms (optional 75) or High Z (Transition Module Dependent)- Additional I/O Options Available
Digital Inputs
Differential RS-422 or TTL; (Optional)

Performance
Bit Rate Range
5bps to 20 Mbps (40 Mbps Optional)
Tuning Resolution
X.XXXEN (1
Input Levels
0.1 Vpp Min., ± 12 V Max.. (others available)
DC Offsets
100% of the input peak-to-peak signal level.
AC Offset
No degradation up to 100% of input signal amplitude at 0.1% of the bit rate.
Loop Bandwidths
0.01% to 1.6%
Acquisition Range
2x LBW
Sync Acquisition Threshold
SNR 0 dB
Sync Maintenance
SNR –3dB
Sync Acquisition
&alt; 50 bits
Sync Retention
256 bits without transitions
Bit Error Rate
1 dB to 40 Mbps

Features
Input/Output PCM Codes
NRZ-L/M/S, BIØ-L/M/S, DBIØ-M/S, DM-M/S; MDM-M/S
Randomizer/Derandomizer
IRIG 106-96 forward and reverse
Descrambler
CCITT V.35/V.36
Viterbi Decoder
R 1/2, K 7 with G1/G2 Swap and G2 Invert, (others available)
Resequencer
QPSK/OQPSK/SOQPSK (Optional)
Frame Pattern Detector
Up to 64 bits with programmable strategy and APC
Auto Scan (Option)
Searches up to 8 Bit Rate, Code, Frame pattern combos per Bit Sync
Output Data Polarity
Input polarity normal / inverted.
Output Clock Phase
0, 90, 180, 270 degrees
BERT Function
Bit-Error-Rate PRN Generator/Error Detector

Outputs, each Bit Sync Channel
TTL (Each Channel)
Two Coded PCM and Two Clocks (Programmable 0, 90, 180, 270 degrees)
2nd Output Per Channel:
RS422 or TTL

Coded PCM and Clock (Programmable 0, 90, 180, 270 degrees)
Bipolar Tape Output
One +/-1V - Coded PCM
Lock Status
Loss and Composite Lock (Bit Sync, Frame Pattern and Viterbi)
Signal Quality Status
Eb/No, Deviation, Frame Sync Pattern Error Count, Viterbi Error Count and BERT / PRN BER Measurements on Front Panel Display and Remote Port
Setup/Control
RS-232(Std), RS-485 (Opt), PCI Bus Control (Opt)