Bit Synchronizers

Model 2365 Multi-Channel PCM Bit Synchronizer
Model 2365 Multi-Channel PCM Bit Synchronizer

The GDP Model 2365 Multi-Channel PCM Bit Synchronizer houses up to 4 high-performance bit synchronizer channels in a 1U chassis. The optimized digital design of this unit affords the highest performance characteristics currently available.

Control and monitoring of all parameters and features is accomplished by way of a “dumb” terminal, mouse and keyboard or a remote computer. The remote computer has access to the unit through an Ethernet interface, RS-232 or IEEE-488 interface.

The bit synchronizer is capable of maintaining synchronization to –3 dBEb/No at signal levels as low as 0.1 Vpp. Search acquisition is attainable in less than 50 bits and synchronization is maintained for a period of at least 256 bit periods without a transition.

Four Analog inputs are provided per channel. Optional digital inputs forRS-422 and TTL levels may be included. Each channel presents a variety of outputs to support complex system requirements.

A standard IRIG randomizer/derandomizer (forward and reverse) is included as is a CCITT V.35 and V.36 scrambler/descrambler. A variety of Viterbi decoders are available including R1/2 K7 (Std), R3/4 K7 andR1/3 k7 (please inquire for other FEC options). Reed Solomon Decoding is an available option.

Automatic Polarity Correction (APC) and an additional level of synchronization assurance is provided by invoking the Frame Pattern Detector.

Data-stream quality is measured and reported to the user in the form of: Eb/No, Frame Synch Pattern Errors, Viterbi Decoder Errors, Bit Error Rate.

A data stream generator / simulator is included to facilitate system testing.

An Auto Scan feature is available that allows the bit synchronizers to scan the input for up to 8 pre-selected bit rates, input codes and frame patterns. When an acceptable signal is present, the Bit Synchronizer automatically locks to it and recovers the data and clock. Should this signal drop-out, the bit synchronizer re-initiates the scan sequence.

  1. Up to 4-Channels in 1U
  2. Bit Rates:
  3.      • 5 bps to 20 Mbps
         • 5 bps to 40 Mbps (Opt)
  4. Performance within 1 dB of theory
  5. Loop Bandwidth Settings from 0.01% to 1.6%
  6.      • Extended LBW Range (Opt)
  7. NRZ-L/M/S, BiØ-L/M/S, DM-M/S; MDM-M/S
  8. Randomizer/Derandomizer
  9. Scrambler/Descrambler
  10. CCITT V.35/36
  11. Viterbi Decoder
  12. Frame Pattern Detector
  13. Input Signal Status
  14.      • Sync and Loss
         • Measured Bit Rate
         • Bit Rate Deviation
         • Measured Signal Level
         • Input Data Polarity
  15. Signal/Data Quality Status
  16.      • Eb/No Measurement
         • Frame Sync Pattern Error Count (BER Status)
         • Viterbi Error Count
         • BERT/ PRN BER Measurement
  17. Date Generator/Simulator
  18.      • Serial and QPSK(Opt)
  19. Advanced Lock Detection
  20. Auto Bit-Rate Scan (Opt)
  21. OPSK/OQPSK/SOQPSK Resequencer (opt)
  22. Remote Control via
  23.      • Ethernet
         • RS-232
         • IEEE-488, (Opt)
  24. 1.75-inch High Chassis
Inputs, each Bit Sync Channel
Analog Inputs
2 Inputs per Bit Sync- 50 ohms (optional 75) or High Z Digital Inputs Differential RS-422 and TTL (Optional)

Bit Rate Range
5bps to 20 Mbps (40 Mbps Optional)
Tuning Resolution
X.XXXEN (1≤N≤7)
Input Levels
0.1 Vpp Min., ± 12 V Max.. (others available)
DC Offsets
100% of the input peak-to-peak signal level.
AC Offset
No degradation up to 100% of input signal amplitude at 0.1% of the bit rate.
Loop Bandwidths
0.01% to 1.6% (Extended LBW Range Optional)
Acquisition Range
2x LBW
Sync Acquisition Threshold
SNR 0 dB
Sync Maintenance
SNR –3dB
Sync Acquisition
< 50 bits
Sync Retention
256 bits without transitions
Bit Error Rate
1 dB to 40 Mbps

Input/Output PCM Codes
IRIG 106 forward and reverse
CCITT V.35/V.36
Viterbi Decoder
R 1/2, K 7 with G1/G2 Swap and G2 Invert, (others available)
Frame Pattern Detector
Up to 64 bits with programmable strategy and APC
Auto Scan (Optional)
Up to 8 preset: Bit Rate, Code, Frame pattern per Bit Sync
Output Data Polarity
Input polarity Normal / Inverted.
Output Clock Phase
0, 90, 180 & 270 degrees to 20 Mbps; 0 & 180 degrees 20Mbps to 40Mbps
BERT Function
Bit-Error-Rate PRN Generator/Error Detector (opt)

Outputs, each Bit Sync Channel
TTL (Each Channel):
Coded PCM and Clock (Programmable 0, 90, 180, 270 degrees )
RS422 (Each Channel):
Coded PCM and Clock (Programmable 0, 90, 180, 270 degrees )
Bipolar Tape Output:
(Each Channel)- ± 1V - Coded PCM
Lock Status:
Bit Synchronization, Frame Pattern and Viterbi
Signal Quality Status:
Eb/No, Deviation, Frame Sync Pattern Error Count, Viterbi Error Count and BERT / PRN BER Measurements on Front Panel Display and Remote Port