The FSD010 is a high performance Frame Synchronizer / Data Decommutator and Data Quality Monitor capable of processing a serial data stream at bit rates up to 25 Mbps.

The synchronization correlators search the input serial data stream for the frame sync pattern in both the normal and complemented form to account for polarity inversions. Up to 64 bits may be included in the pattern with as many as 30 errors allowed by program. A 32K-word instruction memory is programmed with decommutation information for each word in the frame. The serial data is converted to parallel data samples according to this information and is then passed to the parallel output port and/or the optional dual ping-pong data buffer. Each word location of the TDM frame is processed as to: number of bits, parity (test and strip), alignment and its passage to the output or elimination from the output path.

Six 32-bit counters are used to perform Data Quality Monitoring. All counters are active whenever the FSD010 is enabled and can be simultaneously reset by user command. Statistics gathered by the module include: The number of frames received while in sync. Lock, The number of Inverted frames, The number of frames containing a bit-slip, The number of unacceptable sync patterns, The number of transitions from Lock to Search and The number of frames while locked to the Subframe.

Four data words may be selected (based on word & frame number) for capture and presentation for display. The captured words are held in registers that are read by the controlling software. These data are also applied to four 12-bit D-to-A converters. The data are automatically shifted, based on the programmed word size, to align with the DAC MSB.