The GDP Model BSM601 PCM Bit Synchronizer is a state-of-the-art high-performance device that is designed to extract usable digital data from a noise contaminated signal environment. The optimized digital design of this unit affords the highest performance characteristics currently available.

The BSM601 is capable of maintaining synchronization with the signal of interest to Eb/No of -2dB when the signal transition density is 50%. When searching for the signal, acquisition is attainable within 128 bits. The unit maintains synchronization for a period of at least 128 bit periods without a signal transition.

Encoded data streams are processed to expose the raw information. Randomized data is decoded to its native form by a pseudo-random decoder that handles lengths of 2 raised to the power 9, 11, 15, 17, 20 or 23. Both forward and reverse sequences are accommodated. Additionally, a Viterbi decoder (constraint length 7 rate 1/2) is included.

To add accuracy to the bit lock decision, the Viterbi decoder and / or the Frame Pattern Detector may be invoked.

To further assure synchronization to the intended data stream, the Frame Pattern Detector may be invoked. Up to a 32-bit long pattern is detected. Maintaining synchronization with this pattern at the programmed repetition rate produces a lock signal, which may be included in the bit-lock indication.