The GDP Model 2365 Multi-Channel PCM Bit Synchronizer houses up to 4 high-performance bit synchronizer channels in a 1U chassis. The optimized digital design of this unit affords the highest performance characteristics currently available.

Control and monitoring of all parameters and features is accomplished by way of a “dumb” terminal, mouse and keyboard or a remote computer. The remote computer has access to the unit through an Ethernet interface, RS-232 or IEEE-488 interface.

The bit synchronizer is capable of maintaining synchronization to –3 dB Eb/No at signal levels as low as 0.1 Vpp. Search acquisition is attainable in less than 50 bits and synchronization is maintained for a period of at least 256 bit periods without a transition.

Four Analog inputs are provided per channel. Optional digital inputs for RS-422 and TTL levels may be included. Each channel presents a variety of outputs to support complex system requirements.

A standard IRIG randomizer/derandomizer (forward and reverse) is included as is a CCITT V.35 and V.36 scrambler/descrambler. A variety of Viterbi decoders are available including R1/2 K7 (Std), R3/4 K7 and R1/3 k7 (please inquire for other FEC options). Reed Solomon Decoding is an available option.

Automatic Polarity Correction (APC) and an additional level of synchronization assurance is provided by invoking the Frame Pattern Detector.

Data-stream quality is measured and reported to the user in the form of: Eb/No, Frame Synch Pattern Errors, Viterbi Decoder Errors, Bit Error Rate.

A data stream generator / simulator is included to facilitate system testing.

An Auto Scan feature is available that allows the bit synchronizers to scan the input for up to 8 pre-selected bit rates, input codes and frame patterns. When an acceptable signal is present, the Bit Synchronizer automatically locks to it and recovers the data and clock. Should this signal drop-out, the bit synchronizer re-initiates the scan sequence.