The GDP Model 2266 Multi-Channel PCM Bit Synchronizer houses up to eight high performance bit synchronizer modules. The optimized digital design of this unit affords the highest performance characteristics currently available.

The Model 2266 is capable of maintaining synchronization with the signal of interest down to –3 dB Eb/No. When searching for the signal, acquisition is attainable in less than 50 bits. The unit is very robust and can maintain synchronization for a period of at least 256 bit periods without a transition.

The standard IRIG randomizer/derandomizer for both forward and reverse sequences is provided. CCITT V.35 and V.36 scrambling/descrambling is also provided. A variety of Viterbi decoders are available including R1/2 K7 (Std), R3/4 K7 and R1/3 k7 (please inquire for other FEC options).

The MD2265 includes several unique features to determine the quality of the data. The first is an Eb/No (Signal Quality) measurement. From this measurement the error rate of the data can be determined. The BSM201B also measured errors in the frame synchronizer pattern as well as errors in the viterbi stream when these modes are enabled. A bit-error-rate (BERT) function is also provided. This allows link test in a short loop-back to verify proper operation of the module, or long loop-back to measure performance of the link. An advances lock detector ensures a solid lock indication for the module.

To assure synchronization to the intended data stream, the Frame Pattern Detector may be invoked. Up to a 64- bit long pattern is detected. Maintaining synchronization with this pattern at the programmed repetition rate and synchronization strategy produces a lock signal. An Automatic Polarity Correction (APC) mode is also provided for inverted data.

The optional Auto Scan feature is available to scan the input for up to 8 combinations of bit rates, input codes and frame patterns (per Bit Sync channel). When one of the signals is present the Bit Sync automatically locks onto it and recovers the data and clock.